EDA全加器程序分析和总结.docxVIP

library ieee; use ieee.std_logic_1164.all; entity nd1 is port(a,b:in std_logic; c:out std_logic); end nd1; architecture nd1_a of nd1 is begin c=a and b; end nd1_a; library ieee; use ieee.std_logic_1164.all; entity nd2 is port(d,e:in std_logic; f:out std_logic); end nd2; architecture nd2_a of nd2 is s,cout:out std_logic); begin end adder; f=not(d or e); architecture adder_a of adder is end nd2_a; component nd1 is library ieee; port(a,b:in std_logic; use ieee.std_logic_1164.all; c:out std_logic); entity nd3 is end component; port(g,h:in std_logic; component nd2 is l:out std_logic); port(d,e:in std_logic; end nd3; f:out std_logic); architecture nd3_a of nd3 is end component; begin component nd3 is l=g xor h; port(g,h:in std_logic; end nd3_a; l:out std_logic); library ieee; end component; use ieee.std_logic_1164.all; component nd4 is entity nd4 is port(m:in std_logic; port(m:in std_logic; n:out std_logic); n:out std_logic); end component; end nd4; signal r1,r2,r3,r4:std_logic; architecture nd4_a of nd4 is begin begin U1:nd3 port map(x,y,r1); n=not m; U2:nd3 port map(r1,cin,s); end nd4_a; U3:nd1 port map(r1,cin,r2); library ieee; U4:nd1 port map(x,y,r3); use ieee.std_logic_1164.all; U5:nd2 port map(r2,r3,r4); entity adder is U6:nd4 port map(r4,cout); port(x,y,cin:in std_logic; end architecture adder_a;