FPGA可编程规律器件芯片EP2SGX125GF1508C5N中文规格书 .docxVIP

本文格式为Word版，下载可任意编辑 — PAGE \* Arabic 1 — FPGA可编程规律器件芯片EP2SGX125GF1508C5N中文规格书 I/O Structure  Figure2–54.Stratix II IOE in DDR Output I/O Configuration Notes(1), (2)  Notes to Figure2–54:  (1)All input signals to the IOE can be inverted at the IOE.  (2)The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an  inverter at the OE register data port. Similarly, the aclr and apreset signals are also active-high at the input ports of the DDIO megafunction.  (3)The optional PCI clamp is only available on column I/O pins.  Stratix II Device Handbook, Volume 1  Stratix II Architecture Figure2–55.Output TIming Diagram in DDR Mode  The Stratix II IOE operates in bidirectional DDR mode by combining the  DDR input and DDR output configurations. The negative-edge-clocked  OE register holds the OE signal inactive until the falling edge of the clock.  This is done to meet DDR SDRAM timing requirements.  External RAM Interfacing  In addition to the six I/O registers in each IOE, Stratix II devices also have  dedicated phase-shift circuitry for interfacing with external memory  interfaces. Stratix II devices support DDR and DDR2 SDRAM, QDR II  SRAM, RLDRAM II, and SDR SDRAM memory interfaces. In every  Stratix II device, the I/O banks at the top (banks 3 and 4) and bottom  (banks 7 and 8) of the device support DQ and DQS signals with DQ bus  modes of ×4, ×8/×9, ×16/×18, or ×32/×36. Table2–14 shows the number  of DQ and DQS buses that are supported per device.  Table2–14.DQS DQ Bus Mode Support(Part 1 of2)Note(1)  Device Package Number of  ×4Groups  Number of  ×8/×9 Groups  Number of  ×16/×18 Groups  Number of  ×32/×36 Groups  EP2S15484-pin FineLine BGA8400 672-pin FineLine BGA18840  EP2S30484-pin FineLine BGA8400 672-pin FineLine BGA18840  EP2S60484-pin FineLine BGA8400 672-pin FineLine BGA18840  1,020-pin FineLine BGA361884  Stratix II Device Handbook,