DC示例练习笔记.docxVIP

DC 示例练习笔记 1、示例准备 DC 软件； 试验材料准备，构造 risc_design 文件夹 在 Verilog 文件夹下增加 count4.v,count_tb.v 源码文件4）该文件夹复制到虚拟机中 2、示例练习 设置库文件 在自己的工作的文件夹下，使用 design vision 在后台打开 DC 图形界面，file-setup 设置 link library,target library,symbol library 如图，这个库文件在安装目录dc2016/library/syn 文件夹下，复制到自己新建的文件下，在此设置的时候选择即可。 使用菜单 file-read 读入 count4.v count_tb.v 文件，查看 log 打印文件如下 read_file -format verilog {/usr/work/risc_design/source/verilog/count4.v} Loading db file /usr/work/risc_design/libraries/tc6a_cbacore.db Loading db file /usr/synopsys/dc2016/libraries/syn/gtech.db Loading db file /usr/synopsys/dc2016/libraries/syn/standard.sldb Loading link library cba_core Loading link library gtech Loading verilog file /usr/work/risc_design/source/verilog/count4.v Detecting input file type automatically (-rtl or -netlist). Reading with Presto HDL Compiler (equivalent to -rtl option). Running PRESTO HDLC Warning: Cant read link_library file your_library.db. (UID-3) Compiling source file /usr/work/risc_design/source/verilog/count4.v Inferred memory devices in process in routine count4 line 14 in file /usr/work/risc_design/source/verilog/count4.v. =================================================== ============================ | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | =================================================== ============================ | q_reg | Flip-flop | 4 | Y | N | N | N | N | N | N | =================================================== ============================ Presto compilation completed successfully. Current design is now /usr/work/risc_design/source/verilog/count4.db:count4 Loaded 1 design. Current design is count4. design_vision Current design is count4. 设置互连线模型 菜单 attribute-operating environment -wire load ; 4)设置时钟约束 在图形界面的层次化窗口中选中顶层设计，右键选择“”schematic view“”出现如下界面 选中 clk 管脚，然后点击菜单 attributes-specify clk 弹出窗口如下 填写 name 、period、rising、falling 即可约束为时钟周期、上升沿、下降沿。观察命令行打印如下： create_clock -name clk -period 100 -waveform { 0 50 } { m4/clk } 即刚才的设置其实就是这条命令的图形化而已。 5）综合 点击菜单 desig