高等计算机体系结构课件第十章（英文版）.pptxVIP

Caches and 5 Stage Pipelines1 Multistage PipelinePCInstMemoryDecodeRegister FileExecuteDataMemory+4f2dEpochm2wstall?The use of magic memories makes this design unrealistic M12-2 A Simple Memory ModelReads and writes are always completed in one cyclea Read can be done any time (i.e. combinational)If enabled, a Write is performed at the rising clock edge (the write address and data must be stable at the clock edge)MAGIC RAMReadDataWriteDataAddressWriteEnableClockIn a real DRAM the data will be available several cycles after the address is suppliedM12-3 Memory Hierarchy size: RegFile SRAM DRAM latency: RegFile SRAM DRAM bandwidth: on-chip off-chip On a data access:hit (data ? fast memory) ? low latency accessmiss (data ? fast memory) ? long latency access (DRAM)Small,Fast MemorySRAMCPURegFileBig, Slow MemoryDRAMholds frequently used datawhy?M12-4 Inside a CacheCACHEProcessor MainMemory AddressAddressDataDatacopy of main memlocations 100, 101, ... Address TagData BlockDataByteDataByteDataByteLine = Add tag, Data blk1003046848 416How many bits are needed for the tag?Enough to uniquely identify blockM12-5 Cache ReadSearch cache tags to find match for the processor generated address Found in cache a.k.a. HITReturn copy of data from cacheNot in cachea.k.a. MISSRead block of data from Main Memory – may require writing back a cache lineWait … Return data to processor and update cacheWhich line do we replace?M12-6 Write behaviorOn a write hitWrite-through: write to both cache and the next level memoryWriteback: write only to cache and update the next level memory when line is evacuatedOn a write miss Allocate – because of multi-word lines we first fetch the line, and then update a word in itNot allocate – word modified in memoryM12-7 Cache Line SizeA cache line usually holds more than one wordReduces the number of tags and the tag size needed to identify memory locationsSpatial locality: Experience shows that if address x is referenced then address