ethmac10g高速以太网verilog源代码及验证模型详细设计说明receive.pdfVIP

1 Introduction The describes the design of the receive engine used in the Opencores 10-Gigabit Ethe project. This design is designed to 10-Gigabit Ethe IEEE 802.3 ae-2002. It is essentially a faster version of the Ethe where half duplex operat