VHDL与数字电路设计课件.pptVIP

我們曾舉過一個二輸入的與門電路的例子： Library ieee; Use ieee.std_logic_1164.all; Entity and2 is Port(d1,d2 : in std_logic; op : out std_logic); End and2; Architecture m1 of and2 is Begin op= ‘1’ when(d1=’1’ and d2=’1’)else ‘0’; End m1; Library ieee; Use ieee.std_logic_1164.all; Entity mux is Port(a,b,c : in bit; p1,p2 : in bit z : out bit); End and2; Architecture m1 of mux is Begin z= a when p1=‘1’ else b when p2=‘1’ else c; End m1; 允許有重疊 三、選擇式信號設置語句：With-Select-When With expression Select 賦值目標=運算式