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- 约1.89千字
- 约 22页
- 2024-01-03 发布于湖北
- 举报
信号与变量;非静态与静态数据对象;常量;信号;计数向量中‘1’的个数;libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
entitycount_onesis
port(din:instd_logic_vector(7downto0);
ones:outintegerrange0to8);
endcount_ones;
architecturenot_okofcount_onesis
signaltemp:integerrange0to8;
begin
process(din)
begin
temp=0;
foriin0to7loop
if(din(i)=1)then
temp=temp+1;
endif;
endloop;
ones=temp;
endprocess;
endarchitecturenot_ok;;process(clk,clr)
variablecount2:integerrange0to7;
begin
if(clr=1)then
count1=0;
count2:=0;
out1=0;
out2=0;
else
if
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