VHDL语言-矩阵键盘代码键盘.docxVIP

libraryieee;

useieee.std_logic_1164.all;

entitykeyis

port(

clk:instd_logic;

line:instd_logic_vector(3downto0);

row:outstd_logic_vector(3downto0);

key_num:outstd_logic_vector(3downto0);

int:outstd_logic

);

endkey;

architectureaofkeyis

signalkey_num_temp:std_logic_vector(3downto0);

signalstate1:std_logic_vector(1downto0);

begin

process(clk)

begin

if(clkeventandclk=1)then

row=0000;

if(line/=1111)then