VHDL程序集锦分析和总结.docxVIP

组合逻辑：

最高优先级编码器

--HighestPriorityEncoder

--downloadfrom

LIBRARYieee;

USEieee.std_logic_1164.ALL;entitypriorityis

port(I:inbit_vector(7downto0);--inputstobeprioritisedA:outbit_vector(2downto0);--encodedoutput

GS:outbit); --groupsignaloutput

endpriority;

architecturev1ofpriorityisbegin

process(I)begin

GS=1;--setdefaultoutputsA=000;

ifI(7)=1then

A=

111;

elsif

I(6)=

1then

A=

110;

elsif

I(5)=

1then

A=

101;

elsif

I(4)=

1then

A=

100;

elsif

I(3)=

1then

A=

011;

elsif

I(2)=

1then

A=

010;

elsif

I(1)=

1then

A=

001;

elsif

I(0)=

1