VHDL语言编写DS18B20温度传感器程序.pdf

VHDL语言编写DS18B20温度传感

器程序

RevisedonJuly13,2021at16:25pm

VHDL语言编写DS18B20温度传感器程序

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_UNSIGNED.ALL;

entityds18B20is

portclk:instd_logic;50MHz

dq:inoutstd_logic;

rst:instd_logic;

LED:outstd_logic;

LED2:outstd_logic;

LED3:outstd_logic;

dataout1;dataout2;dataout3:outstd_logic_vector6downto0;--数

endds18B20;

architectureBehavioralofds18B20is

TYPESTATE_TYPEis

RESET;CMD_CC;WRITE_BYTE;WRITE_LOW;WRITE_HIGH;READ_BIT;

CMD_44;CMD_BE;WAIT800MS;GET_TMP;WAIT4MS;

signalSTATE:STATE_TYPE:=RESET;

signalclk_temp:std_logic:=0;

signalclk1m:std_logic;--分频后得到的1M时钟

signalcp:std_logic;--1ms时钟

signalw:integerrange0to2:=0;xianshishunxusignalw:integerrange0to2:=0;xianshishunxu

signalTMP:std_logic_vector11downto0;

signaltmp_bit:std_logic;

signalWRITE_BYTE_CNT:integerrange0to8:=0;

signalWRITE_LOW_CNT:integerrange0to2:=0;

signalWRITE_HIGH_CNT:integerrange0to2:=0;

signalREAD_BIT_CNT:integerrange0to3:=0;

signalGET_TMP_CNT:integerrange0to13:=0;

signalcnt:integerrange0to100_001:=0;

******************************

signalcnt2:integerrange0to4000001:=0;

signaltemp:std_logic;

signaldata_temp0:std_logic_vector15downto0;

signaldecimal0:std_logic_vector15downto0;

signaldecimal1:std_logic_vector15downto0;

signaldecimal2:std_logic_vector15downto0;

signaldecimal3:std_logic_vector15downto0;

signaldata_temp1:std_logic_vector7downto0;

signalinteger0:std_logic_vector7downto0;

signalinteger1:std_logic_vector7downto0;

signalinteger2:std_logic_vector7downto0;

signalinteger3:std_logic_vector7downto0;

signalinteger4:std_logic_vector7downto0;

signalinteger5:std_logic_vector7downto0;

signalinteger6:std_logic_vector