VHDL双语教学第6章.pptVIP

VHDLSimulationSynthesis

AgendaOtherFeaturesinVHDLGenerateAssertFunctionOverloadingFILEIO

GenerateExample(1)ram32:ram_0:static_ramportmap(cs_b,we_b,oe_b,

abus(7downto0),

dbus(7downto0));ram_1:static_ramportmap(cs_b,we_b,oe_b,

abus(7downto0),

dbus(15downto8));ram_2:static_ramportmap(cs_b,we_b,oe_b,

abus(7downto0),

dbus(23downto16));ram_3:static_ramportmap(cs_b,we_b,oe_b,

abus(7downto0),

dbus(31downto24));endgenerateram32;RAM0RAM1RAM2RAM38-bitBus8-bitBus8-bitBus8-bitBus32-bitBus8-bitaddr8-bitaddr8-bitaddr8-bitaddr

GenerateExample(2)ram32:foriin3downto0generateram:static_ramportmap(cs_b,we_b,oe_b,

abus(7downto0),

dbus(8*i+7downto8*i));endgenerateram32;RAM0RAM1RAM2RAM38-bitBus8-bitBus8-bitBus8-bitBus32-bitBus8-bitaddr8-bitaddr8-bitaddr8-bitaddr

GenerateLabel:forParameterNameinRangegenerate ConcurrentStatements...endgenerate[Label];Label:ifConditiongenerate ConcurrentStatements...endgenerate[Label];

GenerateExample(3)Addera(0)

a(1)

a(2)

…

a(wid-1)

b(0)

b(1)

b(2)

…

b(wid-1)sum(0)

sum(1)

sum(2)

…

sum(wid-1)

carry………HAFAFAFAa(0)

b(0)

c_in(1)a(1)

b(1)

c_in(2)

a(2)

b(2)

c_in(3)c_in(win-1)

a(wid-1)

b(wid-1)sum(0)

sum(1)

sum(2)

sum(wid-1)

carry

…

GenerateExample(4)adder:foriin0towid-1generate ls_bit:ifi=0generate

ls_cell:HA

portmap(a(0),b(0),sum(0),c_in(1));

endgeneratelsbit; middle_bit:ifi0andiwid-1generate

middle_cell:FA

portmap(a(i),b(i),c_in(i),sum(i),c_in(i+1));

endgeneratemiddle_bit; ms_bit:ifi=wid-1generate

ms_cell:FA

portmap(a(i),b(i),c_in(i),sum(i),carry);

endgeneratems_bit;endgenerateadder;HAFAFAFAa(0)