SoC设计方法与实现第四章 架构设计.pptVIP

第四章SoC架构设计及ESL设计1

OutlinesSystemdesignCommonlyusedcoresandbusesWhatWhyESLdesignESLdesignMethodologyESLdesignstagesTransactionLevelModelingandstandardWhatESLdesigntooldoSummary

ExampleofHardwareSystemArchitectureSource:ARMLtd.

SoCdesignincludesSystemarchitecturedesignSoftwarestructuredesignHardwaredesign(chipdesign)

KeysystemArchitectureQuestionsApplicationanalysisWhichprocessorshouldIchoose?Hardware/SoftwarepartitioningWhatisinhardware,whatisinsoftware?BusandmemoryarchitectureHowdoIimplementthecontrolstream?HowdoIimplementthedatastream?

CommonlyUsedCoresDSPsARM〔AdvancedRISCMachines)RISCarchitectureARM7,ARM9,ARM10,ARM11MIPS(Microprocessorwithoutinterlockedpipedstages)RISCarchitectureMIPS32,MIPS64PowerPC(DevelopedbyIBM、Motorola、Apple)TI’sDSPTMS320C54,TMS320C55,TMS320C62,TMS320C64ADI’sDSPADSP-21,SHARC,TigerSHARC,BlackfinFreescale’sDSPDSP56300,StarCore

CommonlyUsedBusesARM’sAMBA

CommonlyUsedBuses–cont.IBM’sCoreConnect

CommonlyUsedBuses–cont.Silicore’sWishbone4kindofinterconnections:Point-to-point,dataflow,sharedbus,crossbarswitch

OCP(OpenCoreProtocol)Bus

AvalonBusDevelopedbyAlteraforNioscoreonFPGA

Multi-processorSoC(MPSoC)TI’sDaVinci:ARM+DSPBlockdiagramofTMS320DM6446/3formultimediaapplication

Source:TI

MPSoC–cont.TI’sDaVinci:SourcesharingandcommunicationbetweentwocoresSource:TI

OutlinesSystemdesignCommonlyusedcoresandbusesWhatWhyESLdesignESLdesignMethodologyESLdesignstagesTransactionLevelModelingandstandardWhatESLdesigntooldoSummary

SystemlevelDesignChallengesHowdoIunderstandperformanceofkeyIPblocksbeforedesigning?System-on-ChipdoesnotmeantosimplyputIPintoachipHowtobuildanoptimizedsystem?Asystemmeanssoftware+hardware

ComplexityDriveESLDesign90nmSoCTwoorthreeofmicroprocessorsandmoreDSPsConsiderablymorememoryMorecomplexcommunication