代码转换电路.pdf

libraryieee;

useieee.std_logic_1164.all;

entityand_gateis

port(op1,op2:instd_logic;

and_result:outstd_logic);

endand_gate;

architecturebehaveofand_gateis

begin

and_result=op1andop2;

endbehave;

libraryieee;

useieee.std_logic_1164.all;

entityxor_gateis

port(op1,op2:instd_logic;

xor_result:outstd_logic);

endxor_gate;

architecturebehaveofxor_gateis

begin

xor_result=op1orop2;

endbehave;

libraryieee;

useieee.std_logic_1164.all;

entityhalf_adderis

port(a1,a2:instd_logic;

s,c:outstd_logic);

endhalf_adder;

architecturestructofhalf_adderis

signalb1,b2:std_logic;--说明设计实体中使用的信号

componentand_gate--说明元件“与门”and_gate

port(op1,op2:instd_logic;

and_result:outstd_logic);

endcomponent;

componentxor_gate--说明元件“或门”or_gate

port(op1,op2:instd_logic;

xor_result:outstd_logic);

endcomponent;

begin

G1:and_gateportmap--对“与门”and_gate的一次例化

(op1=a1,

op2=a2,

and_result=c);

G2:xor_gateportmap--对“或门”or_gate的一次例化

(op1=a1,

op2=a2,xor_result=s);

endstruct;