i o处理器体系结构核心计时器3jtag控制运动8sharc aug 1外设-sru.pptx

I/OProcessor

SHARC?architecture2I/OProcessorwith31DMAChannelsCoreTimerTimers(3)JTAGControl400MHzSIMDSHARCCORESports(8)Interrupts(10)8ChannelSampleRateConversion(-128dB)New/EnhancedPeripheralsforSHARCLX3UARTs(2)I2CGPIO(20)6MbitROM2MbitSRAMOn-chipMemorymGPIO/Flags/IRQDigitalAudioInterfaceDigitalPeripheralInterfaceSPI(2)32-BitExternalMemoryInterfaceS/PDIFTx/RxPrecisionClockGenerators(4)InputDataPort/PDAP

BlockDiagram(forADSP-21367/8/9)

I/OProcessorfunctionsManagesDirectMemoryAccessing(DMA)ofprocessormemoryforvarioustransfers.Internalmemory?externalmemoryorexternalperipheralsInternalmemory?externalmemorydevices(throughtheexternalport)Internalmemory?digitalaudiointerface(fromEX4)Internalmemory?digitalperipheralinterfaces(fromLX3)Internalmemory?serialportI/OInternalmemory?serialperipheralinterfaceI/OInternalmemory?UARTI/OInternalmemory?internalmemoryFreestheprocessorcore,allowingittoperformotheroperationswhileoff-chipdataI/Ooccursasabackgroundtask.CoreandDMAshouldaccessdifferentblocksofmemoryforbetterperformance.

GeneralprocedureforusingI/OprocessorDeterminewhichDMAoptionsyouwanttouse:IOP/Coreinteractionmethod–Interruptdrivenorstatusdriven(polling).DMAtransfermethod–ChainedorNonchained.Channelpriorityscheme–Fixedorrotating.DeterminehowyouwanttheDMAtooperate:Determineandsetupthedata’ssourceand/ordestinationaddresses(INDEX).SetupthewordCOUNT(databuffersize).ConfiguretheMODIFYvalues(stepsize).Configuretheperipheral(s):Serialports(SPORTs)Parallelport/ExternalportInputdataport(IDP)UARTSerialPeripheralInterface(SPI)EnableDMASettheapplicablebitsintheappropriatecontrolregisters

TypesofDMANon-chainedDMATostartanewDMA,programmustfirstcleartheDMAenablebit,writenewparameterstotheindex,modify,andcountregisters,thensettheDMAenable