基于源同步接口高速电路时序分析与约束.pdfVIP

简要介绍读写结构

源同步简介

写约束

读约束

更多约束

时序分析

©

2009

Altera

Corporation

Altera、Stratix、Cyclone、MAX、HardCopy、Nios、Quartus

和

MegaCore

是

Altera

Corporation

的商标

2

Briefintroductiontowrite/readstructure

SourceSynchronousIntroduction

Writeconstraints

Readconstraints

Moreconstraints

TimingAnalysis

©2009AlteraCorporation

Altera,Stratix,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearesofAlteraCorporation

2

DDR2

SDRAM

写接口

VCC

输入DDRDQS

时钟