【精品】lab2.pdfVIP

Getting Started with Xilinx System Generator Getting Started with Xilinx System Generator Introduction This lab will introduce students to the basic concepts of creating a design using System Generator within the model based design flow provided through Simulink. The design is a simple multiply- add circuit. Note: There is a completed example in lab2/solutions folder Objectives After completing this lab, you will be able to: • Understand the basics of building a design in System Generator • Simulate a design in System Generator • Run the System Generator token to generate a Xilinx FPGA bitstream • Create a subsystem • Improve performance using dedicated Xilinx FPGA math functions Lab Setup The following software is required to be installed on your system to successfully complete this lab 1. System Generator 8.2 2. ISE 8.2.01 3. ISE CORE Generator IP Update 1 4. MATLAB / Simulink R2006a Creating a 12 x 8 MAC 05b-3 Using the Xilinx System Generator 1-877-XLX-CLAS Procedure 1. Launch the MATLAB program and once invoked change the working directory to: C:\SysGen_Training_Labs\lab2 2. Open the file “lab2.mdl” and observe the following design Figure 1 – Simulink Executable Spec for a multiply-add circuit Note: This design is an executable specification creating in Simulink using the standard blockset. It is a simple multiply-add circuit but serves to demonstrate many of the key concepts of model based design. We are going to design a Xilinx FPGA to this spec 3. Simulate the design for 100 cycles by pre