【精品】lab3.pdfVIP

Signal Routing Getting Started with Xilinx System Generator Introduction In this lab you will design and verify padding and unpadding logic using the System Generator signal routing blocks Objectives After completing this lab, you will be able to: • Understand how signal routing blocks can be used to modify bit individual bits of a signal Lab Setup The following software is required to be installed on your system to successfully complete this lab 1. System Generator 8.2 2. ISE 8.2.01 3. ISE CORE Generator IP Update 1 4. MATLAB / Simulink R2006a Creating a 12 x 8 MAC 05b-3 Using the Xilinx System Generator 1-877-XLX-CLAS Procedure Part 1 – Designing Padding Logic 1. Launch the MATLAB program and once invoked change the working directory to: C:\SysGen_Training_Labs\lab3 2. Launch the Simulink library browser by clicking on the Simulink icon on the MATLAB toolbar 3. Open a new Simulink design sheet by clicking on the “Create new Model” icon from the Simulink Library toolbar 4. Create the design shown in Figure 1 . Use a constant from the Simulink “sources” blockset and a display block from the Simulink “sinks” blockset. Set the value of the constant to .5. Add a Xilinx Gateway In block quantized to “fixed_8_6”. Remember that a System Generator token will also be required in this diagram. Figure 1 – Constant of .5 quantized to fixed [8 6] The objective of this lab is to convert the binary representation of the number .5 when quantized to fixed [8 6] To the number .007813 when quantized to fixed [12 1 1] To accomplish this we are going to have to zero pad the MSBs and reinterpret the num