ArithmeticLogical资料.pptVIP

Modern Microprocessor Architectures: Evolution of RISC into Super-Scalars byProf. Vojin G. Oklobdzija Outline of the Talk Definitions Main features of RISC architecture Analysis of RISC and what makes RISC What brings performance to RISC Going beyond one instruction per cycle Issues in super-scalar machines New directions What is Architecture ? The first definition of the term “architecture” is due to Fred Brooks (Amdahl, Blaaw and Brooks 1964) while defining the IBM System 360. Architecture is defined in the “principles of operation” which serves the programmer to write correct time independent programs, as well as to an engineer to implement the hardware which is to serve as an execution platform for those programs. Strict separation of the architecture (definition) from the implementation details. How did RISC evolve ? The concept emerged from the analysis of how the software actually uses resources of the processor ( trace tape analysis and instruction statistics - IBM 360/85) The 90-10 rule: it was found out that a relatively small subset of the instructions (top 10) accounts for over 90% of the instructions used. If addition of a new complex instruction increases the “critical path” (typically 12-18 gate levels) for one gate level, than the new instruction should contribute at least 6-8% to the overall performance of the machine. Main features of RISC The work that each instruction performs is simple and straight forward: the time required to execute each instruction can be shortened and the number of cycles reduced. the goal is to achieve execution rate of one cycle per instruction (CPI=1.0) Main features of RISC The instructions and the addressing modes are carefully selected and tailored upon the most frequently used ones. Trade off: time (task) = I x C x P x T0 I = no. of instructions / task C = no. of cycles / instruction P = no. of clock periods / cycle (usually P=1) T0 = clock period (nS) What makes architecture RISC ? Load / Store : Regis