原创力文档- 1、原创力文档（book118）网站文档一经付费（服务费），不意味着购买了该文档的版权，仅供个人/单位学习、研究之用，不得用于商业用途，未经授权，严禁复制、发行、汇编、翻译或者网络传播等，侵权必究。。
- 2、本站所有内容均由合作方或网友上传，本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺！文档内容仅供研究参考，付费前请自行鉴别。如您付费，意味着您自己接受本站规则且自行承担风险，本站不退款、不进行额外附加服务；查看《如何避免下载的几个坑》。如果您已付费下载过本站文档，您可以点击 这里二次下载。
- 3、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等，请点击“版权申诉”（推荐），也可以打举报电话：400-050-0827(电话支持时间：9:00-18:30)。
- 4、该文档为VIP文档，如果想要下载，成为VIP会员后，下载免费。
- 5、成为VIP后，下载本文档将扣除1次下载权益。下载后，不支持退款、换文档。如有疑问请联系我们。
- 6、成为VIP后，您将拥有八大权益，权益包括：VIP文档下载权益、阅读免打扰、文档格式转换、高级专利检索、专属身份标志、高级客服、多端互通、版权登记。
- 7、VIP文档为合作方或网友上传，每下载1次， 网站将根据用户上传文档的质量评分、类型等，对文档贡献者给予高额补贴、流量扶持。如果你也想贡献VIP文档。上传文档
查看更多
赣南师院
物理与电子信息学院
设计报告书
姓名：
班级：
学号：
指导老师： 陈 建 萍
时间：
目 录
摘要 ······················································································ 1
·················································································· 1
1 引言···················································································· 2
2 时序逻辑电路······································································ 3
2.1 时序逻辑电路概述······························································ 3
2.2 同步时序逻辑电路的一般设计方法········································· 4
3 设计·················································································································································· 5 3.1.1 同步二进制加法计数器的原理········································· 5
3.2 二进制计数器设计······························································ 6
3.2.1 四位二进制计数器的设计·············································· ··6
4 硬件描述语言VHDL设计及仿真·········································· ·8
4.1：用VHDL设计四位二进制加法计数器········································8
4.2：仿真················································································· 9
4.2.1仿真波形·········································································9
4.2.2时序分析·········································································10
5 体会与展望 ·········································································参考文献 ································································································································································· 13
同步进制加法计数器的设计与仿真摘 要：关键词VHDL语言， 仿真
Design and simulation of synchronous binary carry counter
Abstract: this paper introduces the ordinary design method of sequential logic circuit at first. Then on the basis of the principle and the structure of synchronous binary counters, I designs up a four binary carry counter. The circuit is designed and the simulation of this circuit is carried out by. According to the res
文档评论（0）