chap1PLL 资料.pdfVIP

電信工程學系 National Chiao Tung University Department of Communication Engineering Phase Locked Loop Frequency Synthesizer Phase Locked Loop Frequency Synthesizer Prof. Yao-Huang Kao (高曜煌) E-mail: yhkao@cc.nctu.edu.tw Tel: 035712121ext 54541 Dep. of Communication Engineering National Chiao-Tung University Hsin-Chu Taiwan, R. O. C. Sep 13, 2004 電信工程學系 National Chiao Tung University Department of Communication Engineering Contents ( Part I-Basis) Contents ( Part I-Basis) • 1. Introduction ( ref: Wolaver Chap1, Best Chap1) – a) Category of PLL – b) Applications of PLL in Modern Receiver. • 2. PLL Static and DC Offset (ref: Wolaver Chap2 and 3) • 3. PLL Modeling and Dynamics (ref: Blanchard chap. 1-3 and Smith Chap9) – a) Type, Order, and Stability – b) Transient Analysis – c) Steady State Error • 4. Design Example (ref: Motorola AN535) • 5. Measurement of PLL Parameters (ref: R. Best, chap.7) • 6. Phase Noise in PLL (ref. Wolaver Chap. 6, J. Smith Chap. 10, and Rohde Chap. 2) 電信工程學系 National Chiao Tung University Department of Communication Engineering Contents (Part II-Circuits) Contents (Part II-Circuits) • 1. VCO and Crystal Oscillators – Roles of Crystal – Overtone and Multiplier – Cross-Coupled VCO • 2. Digital Circuits in PLL – Prescaler – Phase Detectors (Ref: Wolaver Chap. 4, Razavi Chap. 8):Ex-OR, Two- State, and Three State – Charge Pump – Programmable Divider • 3. Fractional N Synthesizer – Integer N Synthesizer – Synthesizer for Communication – Sigma-Delta Scheme 電信工程學系 N