基于FPGA的CAN设计.docVIP

毕业设计说明书 基于FPGA的 CAN总线控制器设计 专 业 电子信息工程 学生姓名 XXX 班 级 BXXX 学 号 XX 指导教师 XX 完成日期 2012年6月2日 基于FPGA的CAN总线控制器设计 摘 要：CAN被称为最有前途的总线之一，但是市面上存在的都是标准定制的CAN控制器芯片，因此从ASIC设计思想出发，基于FPGA设计定制功能的CAN控制器芯片，扩展其功能，是十分有意义的。 的重点是CAN总线控制器的设计，即用Verilog HDL语言完成CAN每个模块的设计能够在FPGA开发平台Quartus上通过仿真验证，证明其正确性。 从CAN控制器底层着手，首先分析领会CAN协议，其次比较分析现有的CAN控制器后，将CAN总线控制器分解成各个相互独立却又相互关联的功能模块，并且对各个功能模块的功能和原理深入的理解。再进一步阐述对各功能模块进行设计的思想及设计流程，进行设计，并且进行仿真。仿真波形分析包括:第一，证明设计出的模块逻辑功能的正确性;第二，通过Quartus软件的自动综合，生成网表之后，仿真证明设计的实际性。CAN总线分解成三大模块：设计寄存器逻辑模块，完成对数据，控制器状态以及处理器命令的的存储和读写功能；设计验收滤波器模块，完成帧的标识符的校验，保证帧的标识符的匹配；设计位流处理器模块，完成控制发送缓冲器、接收FIFO和CAN总线之间的数据流，接受帧发送帧等功能。 关键词:Verilog HDL; FPGA; CAN总线 Design of CAN Bus Controller Based on FPGA Abstract: As one of Field Buses, CAN Bus is widely used in many areas. And it is considered to be one of the most promising Buses. But chips available in the marketare customized with all kinds of standards. So from the idea of developing ASIC, we can make use of FPGA to design an application specific CAN controller, hence to its functions, which is very meaningful. The main purpose is to complete the front-end design of CAN controller using FPGA. That means to complete the RTL-level design of Data Link Layer in CAN Protocol by using Verilog HDL, and to achieve its function, then to evaluate the design through the simulation on the platform Quartus II. In the thesis, our work is started from the lower level. Firstly, we analyze theCAN Protocol. Secondly, we split the entire CAN controller into several moduleswhich are independent but associated with each other. Thirdly, their function andprinciple are introduced. At last, we manage to design the modules in RTL-level, to explain the idea and process, and to improve design for timing correctly by simulation.The simulation is divided into two parts: One is the logic function simulation, theother is simulation including information of the netlist and gate delay. Within the whole design, we split CAN contro