自动打铃系统设计说明书.docVIP

自动打铃系统设计说明书 学 生 姓 名： 肖剑洪 学 号：14102500892 专 业 班 级：电子10-02BF 报告提交日期：2012-11-23 湖 南 理 工 学 院 物 电 学 院 目 录 题目及要求简介······································· 1 1、设计题目············································· 1 2、总体要求简介········································· 1 二、设计方案说明·········································· 1 三、各部分功能介绍及程序································ 3 1、系统框图············································· 3 2、选择的FPGA芯片及配置································ 3 3、各模块（元件）说明··································· 5 四、仿真结果·············································· 8 1、计时进位············································ 8 2、手动校时············································· 8 3、六点整闹铃··········································· 9 五、说明··················································· 10 1、输入激励信号说明···································· 10 2、输出结果说明········································· 10 3、显示部分介绍········································· 10 源程序················································ 11 1、顶层模块············································ 11 2、模式控制子模块······································ 12 3、计时及调整子模块···································· 14 4、闹铃及调整子模块···································· 16 5、显示子模块·········································· 18 参考文献·············································· 21 八、感想与总结··········································· 21  一：设计题目及总体要求简介 1、设计题目：自动打铃系统。为了更好的了解和熟练的使用Quartus软件，以及将上课老师所讲授的内容更好的掌握。提高实际动手和编程能力，以及熟悉FPGA各个芯片的功能。 2、总体要求简介 （1）基本计时和显示功能 ① 24小时制显示 ② 动态扫描显示 ③ 显示格式：88-88-88 （2）能设置当前时间(含时、分) （3）能实现基本打铃功能，上午06:00起床铃，打铃5秒 二、设计方案说明 本次设计主要采用Verilog HDL硬件描述性语言、分模块法设计的自动打铃系统。由于这次用的开发板提供的是50M晶振。 首先要对时钟进行分频，当计时到2FA_F07F时完成1s分频，通过计时到60s产生分钟进位信号，再通过60分钟产生时钟进位信号。最后通过6个寄存器对时分秒进行锁存最终输出到8个数码管上完成显示。 当显示时钟和默认闹钟时钟相等时，驱动打铃模块。通过mode, turn, change 查看闹钟，时钟显示，调整时钟。总体设计图框如图2-1示，系统调整部分软件控制流程示意图如图2-2所示。 图 2 - 1总体设计图框 图 2 - 2部分软件控制流程示意图 各部分功能介绍