CMOS VLSI设计 RTL设计与仿真.pptVIP

Unit 4 CMOS VLSI设计;Unit 1 绪论Unit 2 CMOS电路设计基础Unit 3 CMOS电路的逻辑设计Unit 4 CMOS VLSI设计方法 Chap8 设计模式和设计流程 Chap9 RTL设计与仿真 Chap10 逻辑综合与时序仿真 Chap11 可测试性设计与ATPG Chap12 版图设计与验证;Specification Executable model RTL code Gate-level netlist Cell/interconnect level position Mask-level geometry;RTL Design Simulation : from System Level, then in RTL; Basics of Register-Transfer Level Design ⊙ Datapath and control ⊙ ASM charts RTL Coding（Modeling）with VHDL;Register-transfer level design;Register-transfer level system example;Datapath-control systems (1);Datapath-control systems (2);Alternate datapath-controller systems;Data operators（操作符）;Conditionals and multiplexers; Basics of Register-Transfer Level Design ⊙ Datapath and control ⊙ ASM charts RTL Coding（Modeling）with VHDL;ASM (Algorithmic State Machine) charts (1);ASM (Algorithmic State Machine) charts (2);Sample ASM chart;ASM state;Actions in ASM state;Implementing Actions in ASM state;Datapath from ASM states;Function unit sharing example;Sequences of ASM states;Sequences of ASM states: conditionals;Execution of conditionals;Implementing Conditional（branch）;Extracting datapath and controller;Data path-controller extraction;ASM chart: more… (1);ASM chart: more… (2);基于ASM的RTL设计步骤; Basics of Register-Transfer Level Design ⊙ Datapath and control ⊙ ASM charts RTL Coding（Modeling）with VHDL;Modeling;Structure of a VHDL model;VHDL processes;VHDL processes example;Synchronous process;Combinational process;RTL Design Simulation : from System Level, then in RTL; Simulation原理： clock-cycle based event-driven Simulation方法： Testbench;Register-transfer level simulation;Sample: simulation of a VHDL code;RTL Simulation;Event;Event Propagating ;Event in Timewheel;Order of events evaluation;Event-driven RTL simulation; Simulation原理： clock-cycle based