0.18微米CMOS工艺的射频功率预测可扩展的大信号模型外文原文.pdfVIP

Solid-State Electronics 47 (2003) 77–81 /locate/sse Scaleable large-signal model of 0.18 lm CMOS process for rf power predictions Chin-Wei Kuo, Chao-Chih Hsiao, Chien-Chih Ho, Yi-Jen Chan Department of Electrical Engineering, National Central University, Chungli 32054, Taiwan, ROC Received 17 April 2002; received in revised form 17 June 2002; accepted 19 June 2002 Abstract The design of the radio frequency integrated circuits by CMOS technologies requires an accurate and scaleable model, which can be valid in the GHz range for device non-linear behavior predictions [IEEE Trans Solid State Circuits 35 (2000) 186; IEEE J. Solid-State Circuit 33 (1998) 1510]. A modified 0.18 lm gate-length MOSFET rf large-signal model based on BSIM3v3 is presented. This large-signal model includes the required parasitic components to forecast device dc and rf characteristics. Additionally, the microwave load-pull and digital modulated evaluations have been carried out to verify the accuracy of this model, where a good agreement with experimental results can be achieved. 2002 Elsevier Science Ltd. All rights reserved. Keywords: RFICs; MOSFET; Large-signal model; BSIM 1. Introduction model for digital and analog circuit design [5]. BSIM model is widely accepted as the standard CMOS model Due to the increasing demands of the low cost and for circuit operational frequencies below the GHz op- high-level integration for radio frequency integrated eration. To extend the models availability abov