基于FPGA二维提升小波变换IP.pdfVIP

基金项目:国家 863计划资助项目(项目名称:保密;申请人:张启衡) 基于 FPGA的二维提升小波变换 IP核设计 1、2 1 1 1 欧龙 ,,张启衡 杨洪 ,许俊平1中国科学院光电技术研究所 国家863计划光束控制重点实验室,四川 成都 610209; 2中国科学院研究生院,北京 100039 摘要: 提出了一种高效并行的二维离散提升小波DWT变换结构,该结构只需要 7 行数据 缓存,即可实现行和列方向同时进行滤波变换。采用一种基于 CSD 编码和优化的移位加操 作实现常系数乘法器,整个小波变换插入多级流水线寄存器,加快了处理速度。用 VHDL 设计可自动验证的 testbench,通过 matlab+modelsim联合仿真能方便有效地对 IP核进行验证。 此 IP 核具有 3 个可配置参数,分别为图像尺寸、位宽、小波变换的级数,可方便重用。该 IP核已经在 XC2VP20 FPGA上实现,并能稳定工作在 60MHz时钟频率下,其处理 512 ×512 8bit 图像的速度可达 240帧/s,完全能满足高速图像实时处理要求。 关键词:二维离散小波换;CSD编码乘法器;IP核 中图分类号:TP391文献标识码:A IP Core Design for 2D-Lifting-Based Wavelet Transform Based on FPGA 、 1 2 1 1 Ou long , Yang hong , Xu junping 1 Institute of optics and electronics, the Chinese academy of sciences, national 863 program control Lab. Chengdu China, 610209;2 Graduate school of the Chinese academy of sciences, Beijing 10039 Abstract: A highly efficient, parallel pipelined architecture is proposed for 2D-lifting-based discrete wavelet transform. The architecture can process both the row transform and column transform concurrently via just seven-line buffers. A CSD coding-based and optimized shift-add operations are adopted to implement multiplier with a constant coefficient. Multiple pipeline registers was inserted to the architecture increasing the processing speed. The IP core can be verified efficiently and conveniently via the testbench writing with VHDL based on Matlab+Modelsim. The IP core with three configurable parameters including the size, the bit-width, the level of wavelet, can be reused conveniently, and had been verified at 60MHz clock frequency on XC2VP20 FPGA. It can process 240 frames image of 512 ×512 8bit per second, meeting the request for real time processing of high-peed imageKey Words: 2D-DWT; CSD-based multiplier; testbench; IP Core 引言 小波变换能对信号进行多分辨率的分析,具有良好的时频分析特性,随着理论的不断完 善,小波变换在语音、图像视频等领域得到越来越广泛的应用。但是传统小波变换(第一代 小波)采用卷积运算方法,因而过程复杂,运算量大,实时性差,不利于硬件实现。为此, Sweldens 提出提升算法(第二代小波),该算法较传统小波运算简单,且是原位运算,几 乎不占用系统内存,适合 VLSI实现。 正因为提升算法的这些优良特