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- 约8.6万字
- 约 68页
- 2017-09-13 发布于广东
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DSP外设头文件 (共17个)
(1) DSP28_ADC_H
#ifndef DSP28_ADC_H
#define DSP28_ADC_H
//
// ADC Individual Register Bit Definitions:
struct ADCTRL1_BITS { // bits description
Uint16 rsvd1:4; // 3:0 reserved
Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode
Uint16 rsvd2:1; // 5 reserved
Uint16 CONT_RUN:1; // 6 Continuous run
Uint16 CPS:1; // 7 ADC core clock prescaler
Uint16 ACQ_PS:4; // 11:8 Acquisition window size
Uint16 SUSMOD:2; // 13:12 Emulation suspend mode
Uint16 RESET:1; // 14 ADC reset
Uint16 rsv
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