2013《数字逻辑设计》期末考试-试卷及参考答案-更新.pdfVIP

学院 姓名 学号 任课老师 考场教室__________选课号/座位号 ………密………封………线………以………内………答………题………无………效…… 电子科技大学2012 -2013 学年第 二 学期期 末 考试 A 卷 课程名称：_数字逻辑设计及应用__ 考试形式： 闭卷 考试日期： 20 13 年 07 月 05 日 考试时长：_120___分钟 课程成绩构成：平时 30 %， 期中 30 %， 实验 0 %， 期末 40 % 本试卷试题由___七__部分构成，共__7___页。 题号 一 二 三 四 五 六 七 八 九 十 合计 得分 得 分 I. Fill out your answers in the blanks (3’ X 10=30’) 1. If a 74x138 binary decoder has 110 on its inputs CBA, the active LOW output Y5 should be ( 1 or high ). 2. If the next state of the unused states are marked as “don’t-cares” when designing a finite state machine, this approach is called minimal ( cost ) approach. 3.The RCO_L of 4-bit counter 74x169 is ( 0 or low ) when counting to 0000 in decreasing order. 4. To design a 001010 serial sequence generator by shift registers, the shift register should need ( 4 ) bit at least. 5. One state transition equation is Q* = JQ’+K’Q. If we use T flip-flop with enable to complete the equation， the enable input of T flip-flop should have the function EN = ( JQ’+KQ ). （参见课件Flip-flops Transforming Skills.ppt ） 6. A 4-bit Binary counter can have ( 16 ) normal states at most, 4-bit Johnson counter with no self-correction can have ( 8 ) normal states, 4-bit linear feedback shift-register (LFSR) counter with self-correction can have ( 16 ) normal states. 7. If we use a ROM, whose capacity is 16 × 4 bits, to construct a 4-bit binary code to gray code converter, when the address inputs are 1001, ( 1101 ) will be the output. 8. When the input isof an 8 bit DAC, the corresponding output voltage is 2V. The output voltage is