DYNAMO vs. ADOREA Tale of Two Dynamic Optimizers.pptVIP

Performance of In-Thread Opt. (USIII+) Helper Thread Prefetching for Multi-Core Main thread Second core Prefetches initiated Cache miss avoided L2 Cache Miss time ? First Core Trigger to activate (About 65 cycles delay) Spin Waiting Spin again waiting for the next trigger Performance of Dynamic Helper Thread(on Sun UltraSparc IV+) Evaluation Environment for TLS Benchmarks SPEC2000 written in C, -O3 optimization Underlying architecture 4-core, chip-multiprocessor (CMP) speculation supported by coherence Simulator Superscalar with detailed memory model simulates communication latency models b