第12章 通用异步接收发送器的设计和实现课件.pptVIP

------------------------------------------------------------------------- --Title: Receiving shift register ------------------------------------------------------------------------- process (CLK, rShift) begin if CLK = 1 and CLKEvent then if rShift = 1 then rdSReg = (RXD rdSReg(9 downto 1)); end if; end if; end process; ------------------------------------------------------------------------- 第十二章 UART的设计和实现 ● UART的VHDL设计代码 ------------------------------------------------------------------------- --Title: Incoming Data counter ------------------------------------------------------------------------- process (CLK, dataRST) begin if (CLK = 1 and CLKevent) then if dataRST = 1 then dataCtr = 0000; elsif dataIncr = 1 then dataCtr = dataCtr +1; end if; end if; end process; 第十二章 UART的设计和实现 UART的VHDL设计代码 ● ------------------------------------------------------------------------- --Title: Receiving State Machine controller ------------------------------------------------------------------------- process (CLK, RST) begin if CLK = 1 and CLKEvent then if RST = 1 then strCur = strIdle; else strCur = strNext; end if; end if; end process; 第十二章 UART的设计和实现 ● UART的VHDL设计代码 ------------------------------------------------------------------------- --Title: Receiving State Machine ------------------------------------------------------------------------- process (strCur, ctr, RXD, dataCtr) begin case strCur is when strIdle = dataIncr = 0; rShift = 0; dataRst = 1;CE = 0; ctRst = 1; if RXD = 0 then strNext = strEightDelay; else strNext = strIdle; end if; when strEightDelay = dataIncr = 0; rShift = 0; dataRst = 1; CE = 0; ctRst = 0; if ctr(3 downto 0) = 1000 then strNext = strWaitFor0; else strNext = strEightDelay; end if; when strGetData =CE = 0;dataRst = 0;ctRst = 0; dataIncr = 1;rShift = 1; strNext = strWaitFor0; when strWaitFor0 = CE