高速折叠插值模数转换器设计.pdfVIP

高速折叠插值模数转换器的设计 摘要 随着移动多媒体设备的广泛应用,高速、低功耗、小面积的模数转换器(ADC) 在这些设备中变得越来越重要。 本文主要是研究和设计高速、低功耗、中等分辨率的模数转换器,采用折叠 内插式的模数转换结构。折叠结构模数转换器有着高速的结构特性,同时,它利用 模拟预处理电路减少了模数转换器中比较器的数目和电路的复杂性,有效降低了 电路的功耗和面积。此外,折叠结构模数转换器使用插值电路来产生额外的折叠 信号,形成折叠插值模数转换器,在保持高速特性的同时更进一步的降低了芯片 的功耗和面积。 整个电路采用全差分结构,可以有效的降低系统噪声,提高了输入电压摆幅。 采用分布式采样保持电路消除了折叠结构内在的倍频效应,优化设计了折叠放大 器,使用电阻插值减少电路功耗。采用了新的位同步技术,纠正了粗量化和细量化 由于延时带来的误差。 设计最终完成了8位分辨率的CMOS工艺的模数转换器的设计,采样频率为 200MHz,工作电压为1.8v. 采用联合电子(UMC) 0.18um CMOS标准工艺模型进行 HSPICE仿真分析.结果表明,在输入频率为97MHz时,SNDR大于40dB,功耗为130mW, 达到预期设计目标。 关键词: 模数转换器, 折叠插值, CMOS High Speed Folding and Interpolating ADC Design ABSTRACT With the development of the mobile multimedia, the high speed, low power and small area analog to digital converter (ADC) are becoming more and more important. This dissertation mainly to study and design a high speed, low power and middle resolution ADC, uses folding and interpolating structure. Folding structure ADC has the high speed characteristic, by means of analog preprocessing circuit to reduce the number of comparator and the circuit complexity, at the same time, it reduces the power and chip area. Furthermore, folding ADC employing the interpolation schemes to generate extra folding waveforms, it also can cut down the chip power, area and keep the high speed. This whole circuit use fully differential structure, it reduces the system noise and enlarges the input voltage effectively. A distributed sample-and-hold unit is employed to tackle the frequency multiplication problem, which is intrinsic for all FI ADC. Optimizing the folding amplifier design, and employing the resistor interpolating to reduce the power consumption. A new bit synchronization scheme is proposed to correct the error caused