vhdl时钟.docVIP

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clock is port( clk : in std_logic; clk0 : in std_logic; s : in std_logic_vector(9 downto 0); d : out std_logic_vector(5 downto 0); a_dp : out std_logic_vector(7 downto 0); sound : out std_logic); end entity clock; architecture rtl of clock is component alert is port ( clk2 :in std_logic; clk_o4 :out std_logic; clk_o5 :out std_logic; clk_o6 :out std_logic; clk_o7 :out std_logic ); end component alert; signal a1,a2,a3,a4 :std_logic; signal key :std_logic_vector(3 downto 0):=0000; signal counter_d :std_logic_vector(2 downto 0):=000; signal ds1 :std_logic_vector(3 downto 0):=0000; signal ds2 :std_logic_vector(3 downto 0):=0000; signal ds3 :std_logic_vector(3 downto 0):=0000; signal ds4 :std_logic_vector(3 downto 0):=0000; signal ds5 :std_logic_vector(3 downto 0):=0000; signal ds6 :std_logic_vector(3 downto 0):=0000; signal dsc1 :std_logic_vector(3 downto 0):=0000; signal dsc2 :std_logic_vector(3 downto 0):=0000; signal dsc3 :std_logic_vector(3 downto 0):=0000; signal dsc4 :std_logic_vector(3 downto 0):=0000; signal dsc5 :std_logic_vector(3 downto 0):=0000; signal dsc6 :std_logic_vector(3 downto 0):=0000; signal counter_s :std_logic_vector(9 downto 0):=0000000000; signal sound_s :std_logic; signal issound :std_logic:=0; begin sound=sound_s; buzz1:alert port map(clk0,a1,a2,a3,a4); process(clk) begin if(issound=1 and s(8)=1)then issound=0; end if; if(ds1=dsc1 and ds2=dsc2 and ds3=dsc3 and ds4=dsc4 and ds5=dsc5 and ds6=dsc6)then issound=1; end if; end process; process(issound) is variable count :integer:=0; begin if(issound=1)then if(clk0event and clk0=1)then count:=count+1; if count=30 then sound_s=a1; elsif count60 then sound_s=a2; elsif count70 then sound_s=a3; elsif count90 then s