EDA实验自动售卖机的设计.docVIP

library ieee; use ieee.std_logic_1164.all; entity shouhuoji is port rst,clk,ai,bi,ci,di,ei,fi,ok:in std_logic; xianshi:out integer range 0 to 10; ao,bo,co,warn:out std_logic ; end shouhuo; architecture bhv of shouhuo is type state is s0,s1,s11,s15,s110,s2,s21,s25,s210,s3,s31,s35,s310 ; --设计分13个状态 signal n_s,p_s:state; signal a,b:std_logic; begin process clk,rst variable temp:integer range 0 to 3; begin if rst 1 then p_s s0; --时序进程部分 elsif clkevent and clk 1 then p_s n_s; if a 1 then temp: temp+1; --延时3s代码 if temp 3 then b 1; else b