3VHDL程序设计.pptVIP

VHDL程序设计 目录 第一部分：基本逻辑电路设计 1. 组合逻辑电路设计 1.1 两输入与非门电路设计 1.2 译码器电路设计 1.3 编码器电路设计 2. 时序逻辑电路设计 2.1 时钟信号的VHDL描述 2.2 复位信号的VHDL描述 2.3 触发器电路设计 2.4 寄存器电路设计 2.5 计数器电路设计 1. 组合逻辑电路设计 1.1 两输入 与非门电路设计 【例1－2】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY nand_2 IS PORT(a,b:IN STD_LOGIC; y:OUT STD_LOGIC); END nand_2; ARCHITECTURE behav OF nand_2 IS BEGIN PROCESS(a,b) VARIABLE tmp:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN tmp:=ab; CASE tmp IS WHEN “00” =y=‘1’; WHEN “01” =y=‘1’; WHEN “10” =y=‘1’; WHEN “11” =y=‘0’; END CASE; END PROCESS; END behav; 【例1－3】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY nand_2 IS PORT(a,b:IN STD_LOGIC; y:OUT STD_LOGIC); END nand_2; ARCHITECTURE struct OF nand_2 IS COMPONENT inv PORT(in: IN STD_LOGIC; out: OUT STD_LOGIC); END COMPONENT; COMPONENT and2 PORT(in1,in2: IN STD_LOGIC; out: OUT STD_LOGIC); END COMPONENT; SIGNAL out1:STD_LOGIC; BEGIN u1:and2 PORT MAP(a,b,out1); u2:inv PORT MAP（out1，y）； END struct； 1.2 译码器电路设计 3－8译码器真值表 【例1－4】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY decoder_3_to_8 IS PORT(a,b,c,g1,g2a,g2b: IN STD_LOGIC; y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END decoder_3_to_8; ARCHITECTURE rtl OF decoder_3_to_8 IS SIGNAL indata: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN indata=cba; PROCESS(indata,g1,g2a,g2b) BEGIN IF(g1=‘1’AND g2a=‘0’ AND g2b=‘0’) THEN CASE indata IS WHEN “000” = y =; WHEN “001” = y =; WHEN “010” = y =; WHEN “011” = y =; WHEN “100” = y =; WHEN