Verilog交通灯(模块化).doc

本交通灯由四个模块组成： 1、 顶层例化模块（traffic） 2、 同步时钟模块（mast_clk） 3、 东西方向（traffic_x） 4、 南北方向（traffic_y） module traffic( RESET, CLK, num_x, red_x, green_x, yellow_x, num_y, red_y, green_y, yellow_y ); input RESET; input CLK; output red_x; output green_x; output yellow_x; output red_y; output green_y; output yellow_y; output [4:0] num_x, num_y; wire [6:0] num; mast_clk clk( .CLK(CLK), .RESET(RESET), .num(num) ); traffic_x Xx( .CLK(CLK), .RESET(RESET), .NUM(num), .red_x(red_x), .green_x(green_x), .yellow_x(yellow_x), .num_x(num_x) ); traffic_y Yy( .CLK(CLK), .RESET(RESET), .NUM(num), .red_y(red_y), .green_y(green_y), .yellow_y(yellow_y), .num_y(num_y) ); endmodule module mast_clk( CLK, RESET, num ); input CLK; input RESET; output reg [6:0] num; always @(posedge CLK,negedge RESET) begin if(!RESET) num=0; else if(num==59) num=0; else num=num+1b1; end endmodule module traffic_x( CLK, RESET, NUM, red_x, green_x, yellow_x, num_x ); input CLK; input RESET; input [6:0] NUM; output reg red_x; output reg green_x; output reg yellow_x; output [6:0] num_x; reg [6:0] num_x; parameter [2:0] red =3b001, green =3b010, yellow=3b100; reg [2:0] state,next_state; always @(posedge CLK,negedge RESET) begin if(!RESET) state=red; else state=next_state; end always @(NUM) begin case(state) red:begin if(NUMd29) begin next_state=green; red_x=0; green_x=1; yellow_x=0; num_x=7d54-NUM; end else begin next_state=red;