数字设计基础 双语教学版 教学课件 作者 英Barry Wilknson 双语课件（第9章）.pptVIP

* 9. Introduction to VHDL 9.1 A simple example in VHDL 9.2 Stylistic issues 9.3 The IEEE library 9.4 Conditionals in VHDL 9.5 Handling multi-bit signals 9.1 A simple example in VHDL 1. Entity We will start off with a NAND gate. The first thing is to say what the device looks like to the outside world. This basically means describing its port map, i.e. the signals that flow in and out of it. 9.1 A simple example in VHDL To describe this in VHDL, we use an entity declaration. ENTITY nandgate IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC ); END; Each of the signals in th