Chapter 10Fundamentals of Wafer-Level Packaging.ppt

Chapter 10Fundamentals of Wafer-Level Packaging Jason Mucilli Vincent Wu October 1, 2007 What is Wafer-Level Packaging? IC packaging formed at the wafer level on the wafer in the wafer foundry Front end IC fabrication and back end IC assembly performed at wafer foundry CSP chip-scale package 20% larger than IC’s-done ass single chip packages at IC level, assembled by standard SMT, encapsulated and tested Flip Chip Done at wafer level and solder bonded with face down Wafer level packaging Goes extra step in forming electrical connections on the wafer, assembled face down but with SMT equipment, then encapsulating, testing and singulating as packaged IC’s What is Wafer-Level Packaging? Cont. Today’s wafer and IC packaging vs. new wafer level packaging process: Why Wafer-level packaging? Possible benefits Smallest system size Enabling interconnect continuum from IC to PWB because of thin-film processing Reduced cost of packaging, testing and burn-in because all done at the wafer level Elimination of underfill because compliancy of leads or other ways to achieve reliability Improved electrical performance due to short lead lengths Why Wafer-level packaging? Cont. Size benefits Shrinking size of portable and hand-held electronic devices Ultimate IC packaging option-the package and the area it occupies on the PWB are equal to the size of an IC Why Wafer-level packaging? Cont. Cost benefits-achieved by 2 techniques: Increasing wafer size results in more IC’s per wafer Decreasing feature size on the IC- causes “die-shrinks” which result in more IC’s for a given wafer size Equipment Costs As wafer gets larger, the cost of the equipment also goes up Cost increase is more than offset by increased production capacity Disadvantages Incompatibility of PWB Very high I/O IC’s would require very small solder balls on a very tight pitch Requires very high density PWB to interconnect-expensive Why Wafer-level packaging? Cont. Disadvantages Cont. ALL the IC’s good and bad are