ENEE 440Chapter 7.ppt

ENEE 440Chapter 7 8254 Timer 8254 Register SelectThe 8254 timer is actually 3 timers in one. It is an upgraded version of the 8253 timer which was used in the PC/XT. The PC/AT uses the 8254. The decoding scheme is shown below: -CS A1 A0 REGISTER 0 0 0 Counter 0 0 0 1 Counter 1 0 1 0 Counter 2 0 1 1 Control Register 1 X X 8254 NOT SELECTED 8254 Timer Summary The counters are 16 bits wide. The count is loaded and read 8 bits at a time. The order is always LSB first and then MSB. CLK is the frequency of the input clock. OUT is the output which depends on the mode of operation. GATE disables the counter with 0V and enables it with 5V. 8254 Timer Modes ... MODE 0 Interrupt on terminal count: The output goes high when the counter decrements to zero(TC). This output can be connected to an external device to signal an interrupt. MODE 1 Hardware retriggerable one-shot: Also called programmable one-shot. The output goes low when triggered by a 0-1 pulse applied to the gate input. The output goes high on TC (count down to zero). Retriggerable means that during the count-down another 0-1 pulse can retrigger the counter to reload the initial count and start the count-down again. Thus the width of the output (one-shot) can be increased. 8254 Timer Modes ... MODE 2 Rate Generator: This gives a periodic output whose frequency depends on the number N loaded into the counter. This is a divide by N counter. The output stays high until the counter decrements to 1. The output then goes low for one clock cycle and the counter is reloaded with the initial count N. The cycle is repeated. 8254 Timer Modes ... MODE 3 Square Wave Generator: If N is even, output is high for N/2 clock cycles and low for N/2 pulses. Thus the duty cycle is 50% and it is a divide by N counter. If N is odd then OUT is low for (N-1)/2 clock cycles and