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- 2017-08-17 发布于湖北
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INTEGRATION, the VLSI journal 50 (2015) 107–115
Contents lists available at ScienceDirect
INTEGRATION, the VLSI journal
journal homepage: /locate/vlsi
A fast model for analysis and improvement
of gate-level circuit reliability
Chunhong Chen n, Ran Xiao
Department of Electrical and Computer Engineering, University of Windsor, Ontario, Canada N9B 3P4
a r
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