Address Decoding.ppt

Address Decoding Outline Address Decoding Strategy Full Address Decoding Partial Address Decoding Block Address Decoding Address Decoder Design Goal Understand address decoding schemes Understand address decoder design Reading Microprocessor Systems Design, Clements, Ch. 5.1-5.2 Address Decoding Strategy Map memory to address locations “memory” can be peripheral Implement mapping the address decoder Block mapping memory block spans consecutive addresses feed low-order address bits to chip address inputs memory block is aligned decode high-order bits for chip selects deselected chip tristates data I/O memory block chip selects must be mutually exclusive otherwise chips will fight data bus during read cycle multiple locations will be written on write cycle Full Address Decoding Each memory location corresponds to one address no “don’t care” address bits must decode all address bits use all high-order bits to control chip selects all low-order bits go to chip address inputs Example 2 2Kx16 memory chips at $000000-$000FFE and $001000-$001FFE - word addresses A23-A12 = 000000000000 for first block select A23-A12 = 000000000001 for second block select A11-A01 - feed into chip address inputs Full Addressing Example Memories 10KW ROM 2KW block (ROM1) + 8KW block (ROM2) 2KW RAM 2 words for peripheral 1 (PERI1) 2 words for peripheral 2 (PERI2) Mapping make aligned blocks arbitrary location except ROM1 start at $000000 for reset ROM1 at $000000-$000FFE ROM2 at $00400-$007FFE RAM at $001000-$001FFE PERI1 at $008000-$008002 PERI2 at $008004-$008006 Partial Address Decoding Some address lines not decoded “don’t care” values multiple addresses have same decoding example - 2 2Kx16 memories use A23 to select memory memories are mapped multiple times in memory Advantage cheap Disadvantage multiple mapping - accidental illegal memory access should just have bus error instead Partial Decoding Example Partial decoding decode high order bits (by convention) feed low order bits to chip ad