Address Generation for Nanowire Decoders.ppt

Mar. 2007 Northwestern University, U.S.A. Address Generation for Nanowire Decoders Jia Wang, Ming-Yang Kao, Hai Zhou Electrical Engineering Computer Science Northwestern University U.S.A. Emerging Technologies for Computing Achieving high computing power at a low cost is essential to the success of our modern civilization. CMOS technology scaling – Moore’s Law: exponential increase in computing complexity at lowered cost. Advances in design methodologies: ability to harness the computing complexity. ITRS predicts CMOS is approaching the physical limit. Research new mechanism for information storage/processing. Research appropriate design methodologies. Nanowire crossbars Demonstrated to be feasible. Bi-stable molecular at crossbar junctions for information storage. FPGA-like mechanism (LUT) for information processing. High density and compatible with conventional CMOS Boolean logic. Hybrid System with Nanowire Crossbar Fabricating perfect pattern is almost impossible at nanoscale. Hard to achieve precise interconnects. High defect rate. Require post-fabrication configuration Correct functionality. Defect tolerance. Hybrid system: nanowire crossbar and CMOS Nanowire crossbar: high density of functionalities. CMOS: reliable for configuration and interfacing to conventional systems. Nanowire decoders One mechanism to interface nanowire crossbars with CMOS circuits. Demonstrated to be feasible. Nanowire Decoders Pass-transistor-like structures formed randomly at the contacts of mesowires (CMOS) and nanowires allow mesowires to control the resistance of nanowires. Once a proper internal address is applied, one nanowire connects to external circuits (individually addressable). Motivation Previous works Rachlin et al. [6] provided a theoretical bound on the necessary number of mesowires for the existence of a given number of individually addressable nanowires at a given probability. Chen et al. [7] proposed a heuristic approach for address generation by performing rand