PCI技术综述.ppt

PCI System Block Diagram PCI Local Bus Overview The block diagram shows a typical PCI Local Bus system architecture. In this example, the processor/cache/memory subsystem is connected to PCI through a PCI bridge. This bridge provides a low latency path through which the processor may directly access PCI devices mapped anywhere in the memory or I/O address spaces. Typical PCI Local Bus implementations will support up to four add-in board connectors, although expansion capability is not required. To provide a quick and easy transition from 5V to 3.3V component technology, PCI defines two add-in board connectors: one for the 5V signaling environment and one for the 3.3V signaling environment. A “5 volt” board which plugs into only the 5V connector, a “universal”board which plugs into both 5V and 3.3V connectors, and a “3.3V volt” board which plugs into only the 3.3V connector. 32-Bit vs. 64-Bit Slots/Boards  Data Transfer Rate of Clock Frequency and Bus Width PCI-X Features PCI to PCI Bridge Benefits on PCI to PCI Bridge Benefits on PCI to PCI Bridge (Continued) Benefits on PCI to PCI Bridge (Continued) * 6-April ’06 by Nathan Chien The PCI-X bus is a higher frequency, higher performance, higher efficiency bus compared to the PCI bus. PCI-X supports 8-10 loads or 4 connectors at 66MHz and 3-4 loads or 1-2 connectors at 133MHz. The peak bandwidth achievable with 64-bit 133MHz PCI-X is 1064MBytes/sec. Following the first data phase, the PCI-X bus does not allow wait status during subsequent data phases. Most PCI-X bus cycles are burst cycles and data generally transferred in blocks of no less than 128 Bytes. This results in higher bus unitization. Further, the transfer size is specified in the attribute phase of PCI-X transactions. This allows for more efficient device buffer management. The The PCI Specification theoretically supports 32 devices per PCI bus. This means that PCI enumeration software will detect and recognize up to 32 devices per bus. However, as a