汽车尾灯设计VHDL语言--EDA课程设计.docVIP

汽车尾灯设计VHDL语言--EDA课程设计元件列化部分 Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity tp is ?Port(clk:in std_logic; ?????? Left:in std_logic; ?????? Right:in std_logic; ?????? Brake:in std_logic; ?????? Night:in std_logic; ?????? Ld1,ld2,ld3:out std_logic; ?????? Rd1,rd2,rd3:out std_logic); End; Architecture bh of tp is Signal tmp0,tmp1,tmp2,tmp3,tmp4:std_logic; Signal err0,err1,err2,err3,err4,err5:std_logic; signal bm:std_logic; Begin ?Component sz is ?????? Port(clk:in std_logic; ?????? Cp:out std_logic); ?End component; ?Component ctrl is ?????? Port(left,right,brake,night: in std_logic; ?????? Lp,rp,lr,brake_led,night_led: out std_logic); ?End component; ?Component lc is ?????? Port(clk,lp,lr,brake,night:in std_logic; ?????? Ledl,ledb,ledn:out std_logic); ?End component; ?Component rc is ?????? Port(clk,rp,lr,brake,night:in std_logic; ?????? Ledr,ledb,ledn:out std_logic); ?End component; U1:sz port map(clk,bm); U2:ctrl port map(left,right,brake,night,tmp0,tmp1,tmp2,tmp3,tmp4); U3:lc port map(clk,tmp0,tmp2,tmp3,tmp4,err0,err1,err2); U4:rc port map(clk,tmp1,tmp2,tmp3,tmp4,err3,err4,err5); Ld1=err0 and bm; Ld2=err1; Ld3=err2; Rd1=err3 and bm; Rd2=err4; Rd3=err5; End; 汽车尾灯主控制模块CTRL： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY CTRL IS ?? PORT(LEFT,RIGHT,BRAKE,NIGHT: IN STD_LOGIC; ??????? LP,RP,LR,BRAKE_LED,NIGHT_LED: OUT STD_LOGIC); END ENTITY CTRL; ARCHITECTURE ART OF CTRL IS ?? BEGIN ?? NIGHT_LED=NIGHT; ?? BRAKE_LED=BRAKE; ?? PROCESS(LEFT,RIGHT) ????? VARIABLE TEMP:STD_LOGIC_VECTOR(1 DOWNTO 0); ????? BEGIN ???????? TEMP:=LEFTRIGHT; ???????? CASE TEMP IS ??????????? WHEN 00=LP=0;RP=0;LR=0; ??????????? WHEN 01=LP=0;RP=1;LR=0; ??????????? WHEN 10=LP=1;RP=0;LR=0; ??????????? WHEN OTHERS=LP=0;RP=0;LR=1;????? --输出错误控制信号 ???????? END CASE; ?? END PROCESS; END ARCHITECTURE ART; ? 时钟分频模块SZ： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SZ IS ?? PORT(CLK: IN STD_LOGIC;?????????????????????????? --时钟输入 ??????