Introduction toCMOS VLSIDesignLecture 6 Wires.ppt

6: Wires Introduction toCMOS VLSIDesignLecture 6: Wires David Harris Harvey Mudd College Spring 2004 Outline Introduction Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters Introduction Chips are mostly made of wires called interconnect In stick diagram, wires set size Transistors are little things under the wires Many layers of wires Wires are as important as transistors Speed Power Noise Alternating layers run orthogonally Wire Geometry Pitch = w + s Aspect ratio: AR = t/w Old processes had AR 1 Modern processes have AR ? 2 Pack in many skinny wires Layer Stack AMI 0.6 mm process has 3 metal layers Modern processes use 6-10+ metal layers Example: Intel 180 nm process M1: thin, narrow ( 3l) High density cells M2-M4: thicker For longer wires M5-M6: thickest For VDD, GND, clk Wire Resistance r = resistivity (W*m) Wire Resistance r = resistivity (W*m) Wire Resistance r = resistivity (W*m) R? = sheet resistance (W/?) ? is a dimensionless unit(!) Count number of squares R = R? * (# of squares) Choice of Metals Until 180 nm generation, most wires were aluminum Modern processes often use copper Cu atoms diffuse into silicon and damage FETs Must be surrounded by a diffusion barrier Sheet Resistance Typical sheet resistances in 180 nm process Contacts Resistance Contacts and vias also have 2-20 W Use many contacts for lower R Many small contacts for current crowding around periphery Wire Capacitance Wire has capacitance per unit length To neighbors To layers above and below Ctotal = Ctop + Cbot + 2Cadj Capacitance Trends Parallel plate equation: C = eA/d Wires are not parallel plates, but obey trends Increasing area (W, t) increases capacitance Increasing distance (s, h) decreases capacitance Dielectric constant e = ke0 e0 = 8.85 x 10-14 F/cm k = 3.9 for SiO2 Processes are starting to use low-k dielectrics k ? 3 (or less) as dielectrics use air pockets M2 Capacitance Data Typical wires have ~ 0.2 fF/mm Compare to 2 fF/mm for g