CPLD-VHDL国立新营高工WWW.HYIVS.TNC.EDU.TW沈庆阳.PPT

CPLD-VHDL國立新營高工WWW.HYIVS.TNC.EDU.TW沈慶陽 VHDL範例 真值表 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY true IS Port (a,b,c:in STD_Logic; y:out STD_Logic); End true; ARCHITECTURE a OF true IS Begin Y=((not a) and b and (not c)) or (a and b and (not c)); End a; VHDL範例 解碼器(2對4) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY decoder2_4 IS Port (s1,s0:in STD_Logic; m0,m1,m2,m3:out STD_Logic); End decoder2_4; ARCHITECTURE a OF decoder2_4 IS Begin m0=(not s0) and (not s1); m1= s0 and (not s1); m2= (not s0) and s1; m3= s0 and s1; End a; VHDL範例 4對1多工器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY mux4_1 IS Port(s1,s0,d0,d1,d2,d3:in STD_Logic; Y:out STD_Logic); End mux4_1; ARCHITECTURE a OF mux4_1 IS Begin Y=((not s0) and (not s1) and d0) or (s0 and (not s1) and d1) or ((not s0) and s1 and d2) or (s0 and s1 and d3); End a; VHDL範例 1對4解多工器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY demux1_4 IS Port(d,s1,s0:in STD_Logic; d0,d1,d2,d3:out STD_Logic); End demux1_4; ARCHITECTURE a OF demux1_4 IS Begin d0= d and (not s0) and (not s1); d1= d and s0 and (not s1); d2= d and (not s0) and s1; D3= d and s0 and s1; End a; VHDL行為性描述—並行敘述式指令 條件式的訊號設定敘述:When – Else 訊號Y=訊號A When (條件1) Else 訊號B When (條件2) Else 訊號C; 範例:真值表使用並行敘述When-Else LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY true_table IS Port (x:in STD_Logic_Vector(2 downto 0); y:out STD_Logic); End true_table; ARCHITECTURE a OF true_table IS Begin Y= ‘1’ When x=“010” Else ‘1’ when x=“110” Else ‘0’; End a; VHDL範例 解碼器(2對4)When-Else LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; ENTITY decoder2_4w IS Port (s:in Std_Logic_Vector(1 downto 0); m0,m1,m2,m3:out Std_Logic); End decoder2_4w; ARCHITECTURE a OF decoder2_4w IS Begin m0=‘1’ when s=“00” Else ‘0’; m1=‘1’ when s=“01” Else ‘0’; m2= ‘1’ when s=“10” Else ‘0’; m3= ‘1’ when s