ECE 434Advanced Digital SystemL18.ppt

Jan, 2001 UAH-CPE/EE 422/522 ECE 434Advanced Digital SystemL18 Electrical and Computer EngineeringUniversity of Western Ontario Hardware Testing and Design for Testability Testing during design process use VHDL test benches to verify that the overall design and algorithms used are correct verify timing and logic after the synthesis Post-fabrication testing when a digital system is manufactured,test to verify that it is free from manufacturing defects today, cost of testing is major component of the manufacturing cost efficient techniques are needed to test anddesign digital systems so that they are easy to test Testing Combinational Logic Common types of errors short circuit open circuit If the input to a gate is shorted to ground,the input acts as if it is stuck at logic 0 s-a-0 (stuck-at-0) faults If the input to a gate is shorted to positive supply voltage, the input acts as if it is stuck at logic 1 s-a-1 (stuck-at-1) faults Stuck-at Faults How many single stuck-at faults — 2 (n + 1) — where n is the number of inputs We will assume that there is only one stuck-at-fault active at a time in the whole circuit “SSF” — single stuck-at fault Stuck-at Faults for AND and OR gates Testing an AND-OR Network Path Detection Sensitization: Small Example An Example What is a minimum set of test vectors to test the network below for all stuck-at-1 and stuck-at-0 faults? An Example (cont’d) Step 1: A-a-p-v-f-F, s-a-0 ABCD: 1101 (+) Step 2: s-a-0 for c C=1, p=0, w=1 = ABCD=1011 (*) Step 3: s-a-0 for q C=1, D=1, t=0, s=1 = ABCD=1111 (#) Step 4: s-a-1 for a A=0, B=1, C=0, D=1 = ABCD=0101 () Step 5: s-a-1 for d (%) D=0, C =0, t=1 = ABCD = 1100 Testing Sequential Logic In general, much more difficult than testing combinational logic since we must use sequences of inputs typically we can observe inputs and outputs, not the state of flip-flops assume the reset input, so we can reset the network to the initial state Test procedure reset the network to the initial