Lecture 13 VHDL Structural Modeling.ppt

ECE C03 Lecture 13 Lecture 13 VHDL Structural Modeling Hai Zhou ECE 303 Advanced Digital Design Spring 2002 Outline Structural VHDL Use of hierarchy Component instantiation statements Concurrent statements Test Benches READING: Dewey 12.1, 12.2, 12.3, 12.4, 13.1, 13.2, 13.3. 13.4, 13.6, 13.7. 13.8 A general VHDL design Structural Descriptions A structural description of a system is expressed in terms of subsystems interconnected by signals Each subsystem may be another design (component) or a process Component instantiation and port maps entity entity_name (architecture_identifier) port map ( port_name = signal_name expression open, ); Example of Component Instantiation entity DRAM_controller is port (rd, wr, mem: in bit; ras, cas, we, ready: out bit); end entity DRAM_controller; We can then perform a component instantiation as follows assuming that there is a corresponding architecture called “fpld” for the entity. main_mem_cont : entity work.DRAM_controller(fpld) port map(rd=cpu_rd, wr=cpu_wr, mem=cpu_mem, ready= cpu_rdy, ras=mem_ras, cas=mem_cas, we=mem_we); Example of a four-bit register Let us look at a 4-bit register built out of 4 D latches Behavioral Description of Register Structural Composition of Register Structural VHDL Description of Register Structural VHDL Description of Register Mixed Structural and Behavioral Models Models need not be purely structural or behavioral Often it is useful to specify a model with some parts composed of interconnected component instances and other parts using processes Use signals as a way to join component instances and processes A signal can be associated with a port of a component instance and can be assigned to or read in a process Example of Mixed Modeling: Multiplier Component and Signal Declarations The declarative part of the architecture STRUCTURE contains: component declaration signal declaration Example of component declaration component AND2_OP port (A, B: in bit; Z : out bit); end comp