ARM Series Intro.ppt

ARM Series Intro A Glimpse Of ARM Fundamental Principals And Trend ZuMin(033230) Contents Intro To ARM1-7 RISC In ARM Basic Information Memory Control Method in ARM1176JZ Advanced RISC Machines One of the most famous processor producer Focus on producing RISC Processor Emphasis on Performance—Price—Power Proving Design Technical Support Led the evolution of RISE Processor and still Leading Brief History About ARMS Basic Information Word 32bits in ARM system Half-Word 16bits in ARM system Byte 8bits in ARM system THUMB The microprocessor is compatible to 8/16bits devices because of the THUMB ARM microprocessor has two working conditions ARMTHUMB ARM 32bits Instructions THUMB 16bits Instructions Basic Registers Unranked Register R0-R7 Banked Register R8-R14 PC R15 Current Program Status Register R16 ARM11 Microarchitecture The ARM11, the first implementation of the new ARMv6 Instruction Set Architecture Designed to deliver high-performance – efficiently. The current implementation roadmap defines CPU products running at clock speeds forecast in excess of 1GHz. ROAD MAP Performance Characteristics Memory System of ARM1176JZ Cache Organization MMU TLB DMA - Direct Memory Access TCM - Tightly-coupled memory Write Buffer Cache Organization Separate Instruction and Data Caches in a Harvard arrangement. So both store and load instruction on cost one cycle. Four-way set associative cache of configurable size. The caches are virtually indexed and physically tagged. Both the Instruction Cache and the Data Cache can provide two words per cycle for all requesting sources. Features of the cache system The cache is a Harvard implementation (Separate Instruction and Data Caches ). The other main operations performed by the cache is cache line Write-Back. Cache replacement policies are Pseudo-Random or Round-Robin, Round-Robin uses a single counter for all sets, that selects the way used for replacement. Cache lines ca