第十一讲状态机.pptVIP

第十讲VHDL逻辑系统的状态机设计;为什么要使用状态机;回忆计数器设计;Regs;Regs;Regs;Regs;Regs;Regs;Regs;状态机的表示方法1;方法二：算法流程图;方法三：状态转换图;方法三：状态转换图;状态机的描述方法;定义状态机的状态;定义状态变量;PROCESS(reset,clk) BEGIN IF reset=‘1’ THEN current_state=initial; -- 初始状态 ELSIF clk’EVENT AND clk=‘1’ THEN current_state=next_state; END IF; END PROCESS;;PROCESS (current_state) BEGIN CASE current_state IS WHEN state1= IF (条件1) THEN next_state=状态1; ELSIF (条件2) THEN next_state=状态2; …… ELSE;PROCESS(current_state, 其他输入信号) BEGIN CASE current_state IS WHEN state1= output = xxx; WHEN state2= …… END CASE; END PROCESS;;S1;S1;S1;S1;S1;OUTPUT_GEN: PROCESS (current_state) BEGIN CASE CURRENT_STATE IS WHEN S0 = Z = ‘0’; WHEN S1 = Z = ‘1’; WHEN S2 = Z = ‘1’; WHEN S3 = Z = ‘0’; WHEN others = Z = ‘0’; END CASE;END PROCESS;;LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Moore IS PORT(rst: IN STD_LOGIC; clk: IN STD_LOGIC; X: IN STD_LOGIC; Z: OUT STD_LOGIC); END Moore; ARCHITECTURE behavior OF Moore IS TYPE state_type IS (S0,S1,S2,S3); SIGNAL current_state, next_state : state_type; BEGIN --状态寄存器描述 SYNCH : PROCESS(clk, rst, next_state) BEGIN IF clk’event and clk=‘1’ THEN IF rst=‘1’ THEN current_state =S1; ELSE current_state = next_state; END IF; END IF; END PROCESS;;WHEN S3 = IF X = ‘0’ then next_state = S3; ELSE next_state =S1; END IF; WHEN others = next_state =S1; END CASE; END PROCESS; --输出逻辑描述 OUTPUT_GEN: PROCESS (current_state) BEGIN ;状态机实例—Mealy;S1;S1;S1;S1;S1;OUTPUT_GEN: PROCESS (current_state) BEGIN CASE CURRENT_STATE IS WHEN S0 = IF X = ‘0’ THEN Z = ‘0’; ELSE Z = ‘1’; END IF; WHEN S1 = IF X = ‘0’ THEN Z = ‘0’; ELSE Z = ‘0’; END IF; · · · · · · END CASE;END PROCESS;;LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Mealy IS