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An Introduction to Electronic System Level Design.ppt
An Introduction to Electronic System Level Design 錢偉德 國家晶片及系統中心設計服務組 清大資工系視訊通訊研究室 Trend HW Problems HW is getting more complicated: Multiple processors/autonomous engines for parallelism Sophisticated algorithms for acceleration High throughput and low latency Management of dynamic and static power Smaller chip size SW Problems SW becomes a massive task: SW/HW engineer ratios: Multimedia – 2:1 Networking --3:1 Wireless – 4:1 Need to ensure HW spec is what they want. Need to program for the complicated HW. 80% design is determined when 20% into the project. So better do it earlier. Design Team Hardware Team Components, devices, memory Glue logic, clock tree, bus, PLL, etc. FW/SW Team Device drivers RTOS, application porting System Team Application/algorithm analysis Architecture design System Team Comprehend the system at transaction level Application oriented It is good to understand hardware designing, but it is not a must-to-have. Solve big problems at the design phase, not the verification phase System Design Flow Algorithm Architecture Design Algorithm Design Dataflow Analysis Memory access Low-power Architecture Design Memory infrastructure Bus architecture IP Reuse Cache/DMA Multi-Vdd/Multi-Frequency Platform design Performance evaluation Multi-Core SoC Design Flow Algorithm Design Architecture Design Cycle-Accurate System Modeling Transaction-Level and Cycle-Accurate Modeling RTL Design High-Level Synthesis FPGA Implementation Logic Synthesis Place Route Signal Integrity/IR Drop Typical Project Schedule Time to Market HW/SW Co-design Benefits Simulation Speed Issue To be categorized as a system-level language, the simulation SPEED is the key. The simulation speed should take no 1,000 time slower than the real HW. In another word, 1 second of HW execution time equals 16 minutes and 40 seconds simulation time. To achieve this kind of performance, the system is best modeled in transaction level. Solution: Virtual Platform High-Speed Simulation SystemC-Based M
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