M. Manghisonic,d, L. Rattia,c, V. Reb,c, V. Spezialia,c.ppt

Radiation Tolerance of a 0.18 mm CMOS Process Outline Static characterization: ID-VGS Threshold voltage Signal parameters: transconductance Noise characterization: noise voltage spectra Noise characterization: white noise Noise characterization: 1/f noise Conclusions M. Manghisonic,d, L. Rattia,c, V. Reb,c, V. Spezialia,c a Università di Pavia, Dipartimento di Elettronica, 27100 Pavia, Italy b Università di Bergamo, Dipartimento di Ingegneria, 24044 Dalmine, Italy c INFN, Sezione di Pavia, Pavia 27100, Italy d Studio di Microelettronica, STMicroelectronics, 27100 Pavia, Italy 7th International Conference on Advanced Technology and Particle Physics Villa Olmo, 15-19 October 2001 Submicron CMOS technologies and their radiation hardness Comparison with NMOS and PMOS transistors belonging to a 0.35 mm technology 7th International Conference on Advanced Technology and Particle Physics, Villa Olmo, 15-19 October 2001 Static, signal and noise characterization of irradiated NMOS and PMOS devices belonging to a 0.18 mm process V.Re, Radiation Tolerance of a 0.18 mm CMOS Process Submicron CMOS technologies V.Re, Radiation Tolerance of a 0.18 mm CMOS Process 7th International Conference on Advanced Technology and Particle Physics, Villa Olmo, 15-19 October 2001 High density mixed-signal front-end systems for high granularity detectors (microstrip, pixel) Reduced thickness of the gate oxide: 0.35 mm: tOX=7.2 nm 0.25 mm: tOX=5.5 nm 0.18 mm: tOX=4 nm Improved radiation hardness Present focus: 0.25 mm CMOS Characterization of the following CMOS generation (0.18 mm) V.Re, Radiation Tolerance of a 0.18 mm CMOS Process 7th International Conference on Advanced Technology and Particle Physics, Villa Olmo, 15-19 October 2001 Test and irradiation conditions 0.18 mm CMOS process by ST Microelectronics Standard open structure layout (no special radiation hard technique) Irradiation up to 100 kGy (10 Mrad) with a 60Co source Devices biased during irradiation at normal operating